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Journal of Emerging Trends in Computing and Information Sciences >> Call for Papers Vol. 8 No. 3, March 2017

Journal of Emerging Trends in Computing and Information Sciences

Design and FPGA Implementation of High-speed Parallel FIR Filters

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Author Baolin Hou, Yuancheng Yao, Mingwei Qin
ISSN 2079-8407
On Pages 184-189
Volume No. 4
Issue No. 2
Issue Date March 01, 2013
Publishing Date March 01, 2013
Keywords FIR Filter; Field Programmable Gate Array; High-speed Parallel Structure; Polyphase Filter


Abstract

This paper proposes a novel parallel Finite Impulse Response (FIR) filter, which is based on polyphase decomposition. It can increase the running speed by M times compared with the serial FIR filter, where M is the number of sub-filters, and the parallel FIR filter only introduces very small delay. Firstly the theoretical foundation of parallel FIR filters is analyzed. An example of the floating point parallel 4-channel FIR filter is given to verify the algorithm. Then a direct form structure parallel FIR filter is designed, which has optimum fixed point coefficients. Finally the fixed point of 4-channel parallel FIR filter is implemented in Xilinx’s Virtex-6 Field Programmable Gate Array (FPGA). According to the simulation results, this filter has smaller resource consumption and its sampling rate up to 1GHz.
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