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Journal of Emerging Trends in Computing and Information Sciences >> Call for Papers Vol. 8 No. 3, March 2017

Journal of Emerging Trends in Computing and Information Sciences

Simple, Fast and Synchronous Hybrid Scaling Scheme for the 8-bit Moduli Set

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Author Azadeh Safari, Yinan Kong
ISSN 2079-8407
On Pages 949-956
Volume No. 3
Issue No. 6
Issue Date June 01, 2012
Publishing Date June 01, 2012
Keywords Scaling; Residue Number System (RNS); Chinese Remainder Theorem (CRT); VLSI


Abstract

This paper presents an optimized synchronous hybrid scaling scheme for the 8-bit moduli set f2n ?? 1;2n;2n + 1g. Both Look-up-tables (LUTs) and modular adders are employed efficiently to generate the accurate scaled residues. Reverse conversion from residues to the original binary number is also computed in one residue channel without further hardware cost required. Xilinx device xc6slx4 ?? 3tqg144 has been used with maximum frequency of 120MHz. The implementation results show total 14:15mW on-chip-power consumption for a 8  8 input data in 21ns. Evaluation analysis in terms of complexity and delay shows merits of current design over both LUT and Full- adder (FA) based designs. It shows up to 95.38% savings on complexity over LUT based designs and 87.02% and 69.64% savings on unit gate delay over FA and LUT based designs, respectively.  

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